design of 8 bit shift register using d flip flop | Instantiation of sub blocks in verilog
13:23
YouTubeExplore Electronics
design of 8 bit shift register using d flip flop | Instantiation of sub blocks in verilog
#verilog Shift register design in verilog using flipflops In this video, D flipflop design, Instantiation of sub blocks, arithmetic right shift, logical left shift is explained ******correction in code: In line 18: we have to write " output reg signed [7:0] out; " instead of " output reg [7:0]out; " let us discuss if anything wrong. comment ...
4.4K viewsAug 23, 2021
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